An energy-efficient instruction scheduler design with two-level shelving and adaptive banking yu-lai zhao, xian-feng li, dong tong, and xu cheng 采用兩級緩置和自適應多體技術的能耗有效的指令調度器設計
Mainstream processors implement the instruction scheduler using a monolithic cam-based issue queue, which consumes increasingly high energy as its size scales . in particular, its instruction wakeup logic accounts for a major portion of the consumed energy 調度邏輯主要由喚醒和選擇兩部分構成,而基于cam隊列的喚醒邏輯能耗是主要的,喚醒邏輯的能耗主要來源是發(fā)射隊列中的標簽比較器。